Computer Organization & Memory — Instruction Cycle & Control Unit (Unit 1) Summary & Study Notes

📘 Overview

Computer Organization studies how a processor, memory and I/O work together to execute programs. A program is a sequence of instructions. An instruction combines an operation (what to do) and operand(s) (what to operate on). The set of all instructions a processor can execute is its instruction set.

🧩 Elements of an Instruction

Each instruction typically contains an opcode (operation code), operand references (where source data resides), a result reference (where to store results), and a next-instruction reference (sequencing info). Operands may come from main memory, CPU registers, or I/O devices.

🔤 Instruction Representation & Types

In machine code each instruction is a unique bit pattern; humans often use mnemonics like ADD, SUB, LOAD. Instructions are classified by function (data processing, data storage, data movement, program flow control) and by the number of addresses they specify (3-address, 2-address, 1-address, 0-address). More addresses can make instructions more powerful but increase instruction complexity and register demand.

🧾 Operand Types and Addressing

• Register: Encoded in the instruction, fastest, no bus access, short instruction length. Can be source and destination.
• Immediate: Constant encoded in the instruction (e.g., 8/16/32 bits). No bus access; can only be a source operand.
• Memory: Stored in memory; requires bus transfers and possibly address calculation. The computed location used to access data is the effective address. Addressing modes (direct, indirect, indexed, etc.) affect how the effective address is determined.

➕ Types of Operations

Common operation categories: data transfer, arithmetic, logical, conversion, I/O, system control, and transfer of control (branches/jumps).

⚙️ Control Unit: Functional Role

The Control Unit (CU) orchestrates processor activity. To design/characterize CU functions: 1) identify processor elements; 2) list micro-operations the processor must perform; 3) define CU functions to sequence those micro-operations. Key CU operations include instruction sequencing, register transfers, and executing microinstructions that implement fetch/decode/execute cycles.

🔬 Micro-operations

A micro-operation is an elementary internal operation (register-to-register transfer, ALU operation, memory read/write). Executing a high-level instruction involves a sequence of micro-operations organized into subcycles such as fetch, indirect, execute, and interrupt subcycles.

⏱ Instruction Cycle (Instruction Execution States)

The instruction cycle decomposes execution into a standard sequence of states:

• Instruction Fetch (IF): Read the instruction from memory into the processor.
• Instruction Operation Decoding (IOD / Decode): Determine the operation and operand references.
• Operand Address Calculation (OAC): Compute the effective address if memory/I/O operands are involved.
• Operand Fetch (OF): Retrieve operand(s) from memory or I/O into processor registers.
• Data Operation (DO / Execute): Perform the operation (ALU computation, register transfer, I/O interaction).
• Operand Store (OS): Write results back to memory or output device. Some instructions require repeated or additional OAC/OF/OS steps (multiple operands/results). The instruction cycle may also include an interrupt subcycle when handling external events.

🔁 Indirect Addressing & Indirect Cycle

With indirect addressing, the operand field in the instruction points to a memory location that contains the effective address. This requires an extra memory access called the indirect cycle, which is an additional instruction subcycle to fetch the real operand address into the processor before the normal operand fetch.

🧠 Key Processor Registers Used

• Program Counter (PC): Holds the address of the next instruction to fetch.
• Instruction Register (IR): Holds the instruction most recently fetched.
• Memory Address Register (MAR): Holds the address for memory access operations.
• Memory Buffer Register (MBR) (also called Memory Data Register, MDR): Holds the data being transferred to/from memory. Not all processors use MAR/MBR names, but equivalent buffering is always present.

🔄 Data Flow: Instruction Fetch Sequence

1. PC contains address of next instruction.
2. Address is copied to MAR and placed on the address bus.
3. CU issues a memory read; memory places data on the data bus.
4. Data (instruction) is captured into MBR, then transferred to IR.
5. PC is incremented (or updated) to point to the next instruction. This sequence is implemented via micro-operations controlled by the CU.

🔁 Data Flow: Indirect Cycle Sequence

After fetch and decode, if the addressing mode is indirect:

1. The rightmost bits (address field) of MBR are transferred to MAR.
2. CU requests a memory read for that address.
3. The memory returns the effective address in MBR, completing the indirect cycle.

🧾 Execute Phase Variability

The execute phase depends on the instruction: it may involve register transfers, ALU operations, memory reads/writes, or I/O actions. Complex instructions can require multiple micro-operations and memory accesses.

✅ Summary / Learning Outcomes

After studying this material, you should be able to: describe the instruction cycle, list the processor registers involved in instruction execution, explain the role of the control unit and micro-operations, and contrast operand/address types (register, immediate, memory, indirect).