RISC-V Processor Design & Pipelining — Comprehensive Study Notes Summary & Study Notes

🧩 Core Components of a Computer

A processor's performance is governed by three primary factors: instruction count, clock cycle time, and clock cycles per instruction (CPI). The instruction set architecture (ISA) and the compiler determine the instruction count and instruction mix; the processor implementation determines clock cycle time and CPI. Key hardware building blocks include instruction memory, program counter (PC), register file, Arithmetic Logic Unit (ALU), data memory, and control logic.

📐 Datapath & Control Overview

A datapath orchestrates data flow between functional units under direction from the control unit. Typical datapath operations for RISC-V involve: fetching an instruction, reading registers, performing an ALU operation, accessing memory for loads/stores, and writing results back to the register file. Multiplexors select between alternative data sources; control signals enable and route actions across the datapath.

🔢 Instruction Types in the Simplified RISC-V Implementation

The simplified set used to introduce datapath design commonly includes memory-reference instructions (loads/stores), arithmetic-logical instructions (add, sub, and, or), and a conditional branch instruction (beq). The ISA's simplicity and regularity (fixed-length instructions, few formats) make hardware design and pipelining simpler and more efficient.

🔀 Branch Mechanics & Branch Datapath

Conditional branch instructions (e.g., beq) compare two registers via the ALU. The ALU produces a Zero signal that indicates equality. The branch target address is computed by an immediate-generation unit and an adder that adds a sign-extended and shifted immediate to the PC. The branch offset is shifted left by one bit to create a half-word offset (effectively doubling the range). If the Zero signal indicates equality, the PC is set to the branch target; otherwise the PC increments to the next sequential instruction.

🔗 Combining Datapaths for All Instructions

To execute all instruction types in a uniform datapath, components from memory-reference and arithmetic-logical datapaths are integrated and interconnected via multiplexors and control signals. For single-cycle implementations this often requires separate instruction and data memories so that fetching and data access can occur in the same cycle.

⏱ Single-Cycle Implementation: Limitations

A single-cycle CPU executes every instruction in one clock period, so the cycle must be long enough to accommodate the longest-path instruction (typically a load). Although simple and correct, this design yields poor performance because the long clock cycle penalizes all instructions. This motivates breaking instruction execution into stages (pipelining).

🚂 Pipelining: Concept & Benefits

Pipelining splits instruction execution into stages so multiple instructions overlap in time, analogous to an assembly line. Throughput increases because a new instruction can enter the pipeline each cycle, even though the latency of a single instruction remains unchanged. RISC-V is designed for pipelining (fixed-length instructions and limited formats), which simplifies fetch/decode and stage balancing.

🧭 Five Pipeline Stages

A canonical 5-stage pipeline includes:

• IF — Instruction Fetch
• ID — Instruction Decode / Register File Read
• EX — Execute / Address Calculation
• MEM — Memory Access
• WB — Write-Back Pipeline registers sit between stages to hold intermediate values and control signals so each stage operates on its own data each cycle.

⚠️ Pipeline Hazards

Three main hazards can disrupt pipelined execution:

• Structural hazards: hardware resource conflicts (e.g., limited functional units).
• Data hazards: when an instruction depends on the result of a prior instruction that has not yet written back.
• Control hazards: due to branches altering control flow. Handling hazards is essential to maintain correctness while preserving pipeline performance.

🔁 Forwarding (Bypassing) & Load-Use Hazards

Forwarding supplies results from intermediate pipeline stages directly to later stages that need them, avoiding some stalls. For example, ALU results in EX/MEM can be forwarded to the ALU inputs for the subsequent EX stage. However, load-use hazards remain problematic: when an instruction depends on a value being loaded from memory by the immediately preceding instruction, forwarding cannot provide the data in time and a stall (bubble) is required to wait for the memory read to complete.

🧾 Control Hazards: Stalls and Predictions

Branches cause control hazards. Simple handling uses stalls until the branch outcome is known. More advanced strategies include branch prediction to guess the outcome and fetch speculatively, and architecture-specific mechanisms like the MIPS delayed branch that executes the next sequential instruction regardless of branch outcome to hide the delay.

🛠 Control Signals & Pipeline Registers

Control signals required for later stages are generated during ID and propagated through extended pipeline registers to the EX, MEM, and WB stages. In practice groups of signals (often roughly seven control lines for the last stages) are passed together. A truth table mapping opcode fields to control signal settings is the essential specification for implementing the control unit.

🔍 Hazard Detection & Forwarding Control

Hazard detection logic compares destination registers in pipeline-registers (EX/MEM, MEM/WB) with source registers for the instruction in EX/ID to determine when to forward or when to insert stalls. Typical checks include: if a prior instruction will write to a register that the current instruction reads, and that result is not yet in the register file, forward from EX/MEM or MEM/WB as appropriate. Special care is required to never forward a value to the zero register (x0) since x0 is hardwired to zero and should not be overridden.

🧭 Design Principles & Practical Notes

Keep the ISA simple and regular to ease datapath and pipeline design. Separate combinational logic from state using well-defined clocking and pipeline registers so hardware is predictable. Implement forwarding carefully and include a robust hazard detection unit to identify cases requiring stalls. Finally, balance pipeline stage latencies (e.g., instruction fetch vs. ALU vs. memory) to maximize clock frequency and overall throughput.